1. Field of the Invention
This invention relates to clocking techniques for digital circuits, and more particularly to techniques for transferring data from one clock domain to another clock domain in a digital circuit.
2. Description of the Related Art
Logic functions generally, and the various components of digital logic circuits in particular, can be characterized as either combinational (sometimes referred to as combinatorial) or sequential. Combinational logic circuits provide output signals that are directly related to the current combination of values at the circuit""s inputs, and include logic gates that, generally, perform the Boolean logical operations, e.g., AND, OR and NOT. In contrast, sequential logic circuits provide output signals that depend not only on current input values, but also on previous input values or the present state of the circuit, and are comprised of memory elements, such as flip-flops or registers, that maintain state information, that is, that store a value, and combinational logic.
Sequential logic circuits are further characterized as either asynchronous (unclocked) or synchronous (clocked). While the input signals to an asynchronous sequential logic circuit can change at any time, and thus, the state of the circuit is capable of changing at any time, the input signals to a synchronous logic circuit are capable of changing the state, and thus, the output of the circuit, only at specific times, as determined by a particular clocking or timing methodology.
In general, clocked or synchronous sequential circuits are triggered, that is, they change state, according to clock pulses input to the circuit. As the output of a memory element is a signal representing the current state of the memory element, it follows that the output of a clocked sequential circuit is updated in synchronization with clock pulses provided as input to the circuit. A common timing methodology in the art is edge-triggered clocking, where a memory element is triggered, i.e., the one or more inputs to the memory element are sampled, during either the leading (rising) or trailing (falling) edge of a clock signal supplied as input to the memory element. Thus, for example, a trailing edge triggered D-type flip-flop changes state (e.g. provides the signal supplied to the data input as its output signal) on the trailing edge of a clock signal in transition and maintains that state for one clock cycle, that is, until another trailing edge of a clock signal is detected. When it is desirable for a flip-flop to change state with less frequency than every clock cycle (e.g., when propagational delay of a signal through combinational logic coupled between a first and second flip-flop exceeds the time to complete one clock cycle) a control signal provided as input to the second flip-flop may further control at which trailing edge of a clock signal it may change state, so that it is capable of changing state only after the signal output from the first flip-flop has arrived at one of its inputs.
At the time when a memory element such as a flip-flop or register is triggered by the edge of a clock signal, input signals applied to the memory element should be stable. If one or more inputs to a memory element are changing state at the time at which a clock edge is received (and the inputs sampled), the state and, thus, the output of the memory element, may be unstable. When one or more inputs of a memory element are in transition at the time the memory element is triggered, thereby causing the state and output to be indeterminate, the memory element is said to be in a metastable state.
To avoid metastability, digital logic is designed with a variety of timing requirements in mind. The setup time (tsetup) defines that period of time immediately prior to receiving a clock edge in which inputs to the memory element must be stable and valid, either high or low. Another timing requirement, hold time (thold), defines the period of time immediately following receiving a clock edge in which inputs to the memory element must be stable and valid. Metastability can result if such fundamental timing requirements are not met. Consequently, each input to a synchronous memory element must be stable, that is, maintain a voltage level representing a valid logic value so that a single valid output logic value is detected, for a window of time equal to tsetup+thold in order to avoid metastability. It should be further noted, as is well known to those having ordinary skill in the art, that metastability can manifest itself in many ways, including, but not limited to, an unpredictable output logic value, oscillation of the output value, indeterminate voltage level of the output representing a illegitimate logic value somewhere between a valid high or valid low logic value, and an indeterminate period of instability.
When coupling two or more synchronous digital circuits (or two or more portions of a single digital circuit) together it may not be possible or advantageous for all the logic circuitry involved to derive its clock source from the same clock signal. For example, a host bridge or north bridge integrated circuit for a computer system provides, inter alia, bus control signals and address paths for transfers among a host bus (e.g. the bus over which the computer system""s processor communicates), one or more peripheral buses, and memory. Each of the busses (and the devices associated with those busses) may use a different clock signal frequency. In such a case, a plurality of clocks, each providing a clock signal to an exclusive region of the logic circuitry of a device, or each providing a clock signal to the logic circuitry of separate, external, devices may be employed. Thus, multiple clock domains may exist, either within a single circuit, or between circuits that exchange data. Components of a synchronous logic circuit which derive their clock source from the same clock are in the same clock domain, while components of synchronous logic circuits, or synchronous logic circuits, which derive their clock source from different clocks are in different clock domains.
Signals transferred between a first synchronous logic circuit in a first clock domain and a second synchronous logic circuit in a second clock domain are typically transferred asynchronously. One problem inherent in such a transfer is that a signal transferred from the first synchronous logic circuit may be in transition at the same time a clock signal for the second synchronous logic circuit triggers the memory element receiving the signal from the first synchronous logic circuit, thereby inducing metastability. One method to prevent an asynchronous signal arriving at the second logic circuit from being in transition during triggering of the second logic circuit is to use control signals in the form of a two-way handshake to synchronize the asynchronously transferred signal. Unfortunately, synchronizing signals transferred across a clock domain boundary can create timing delays. For example, data being transferred from a faster clock domain to a slower clock domain may have to be held down for a certain number of clock cycles (or xe2x80x9cclockxe2x80x9d) while the logic in the slower clock domain prepares to receive the data.
Accordingly, it is desirable to have circuitry for transferring data between synchronous sequential logic circuits, each having their own clock domain, whereby metastability is avoided and timing delays associated with the transfer are reduced. Additionally, it is also desirable to have circuitry for transferring data between such synchronous sequential logic circuits without having the logic in either of the clock domains aware of the change in clock frequency or the ratio of clock frequencies.
It has been discovered that a gear box circuit can act as an interface for transferring data from a first clock domain to a second clock domain. The gear box circuit uses a level sensitive memory element coupled to an input selection circuit to receive data from logic in the first clock domain and provide the data to logic in the second clock domain. An input selection signal causes the selection circuit to select the input source for the level sensitive memory element, thereby allowing the proper signal to be provided as output to logic in the second clock domain. Additionally, the gear box can provide the proper output signal for logic in the second domain using circuitry to alternately mask the gear box output. The gear box receives control signals, including for example the input selection signal, from control circuitry. The logic in each clock domain does not have to be aware of the clock frequency on the other side of the gear box, nor does it need to be aware of the ratio of clock frequencies between clock domains. Consequently, the logic in each domain is simplified, the gear box circuit itself can be independent of the gear ratio (i.e., the ratio of clock frequencies), timing delays can be reduced, and metastability can be avoided.
Accordingly, one aspect of the present invention provides an apparatus for transferring data from a first clock domain to a second clock domain. The apparatus includes an input data path, a memory element, an input selection circuit, and an output path. The input data path is operable to receive data from the first clock domain. The memory element includes a data input terminal, an enable input terminal operable to receive a memory element enabling signal, and a data output terminal. The input selection circuit is coupled to the memory element, and includes an input selection circuit input terminal, and an input selection terminal operable to receive an input selection signal. An output signal at the data output terminal of the memory element is alternately responsive and non-responsive to an input signal applied to the input selection circuit input terminal depending upon the input selection signal and memory enabling signal. The output path is coupled to the data output terminal of the memory element and operable to provide the data to the second clock domain.
In another aspect of the invention, an integrated circuit includes a first clock domain circuit portion characterized by a first clock signal having a first frequency, a second clock domain circuit portion characterized by a second clock signal having a second frequency, and a gear box circuit for transferring data from the first clock domain circuit portion to the second clock domain circuit portion. The gear box circuit includes an input data path, a memory element, an input selection circuit, and an output path. The input data path is operable to receive data from the first clock domain circuit portion. The memory element includes a data input terminal, an enable input terminal operable to receive a memory element enabling signal, and a data output terminal. The input selection circuit is coupled to the memory element, and includes an input selection circuit input terminal, and an input selection terminal operable to receive an input selection signal. An output signal at the data output terminal of the memory element is alternately responsive and non-responsive to an input signal applied to the input selection circuit input terminal depending upon the input selection signal and memory enabling signal. The output path is coupled to the data output terminal of the memory element and operable to provide the data to the second clock domain circuit portion.
In still another aspect of the invention, a computer system includes a processor, a memory coupled to the processor, and a north-bridge circuit coupled to the processor and the memory. The north-bridge circuit includes a first clock domain circuit portion characterized by a first clock signal having a first frequency, a second clock domain circuit portion characterized by a second clock signal having a second frequency, and a gear box circuit for transferring data from the first clock domain circuit portion to the second clock domain circuit portion. The gear box circuit includes an input data path, a memory element, an input selection circuit, and an output path. The input data path is operable to receive data from the first clock domain circuit portion. The memory element includes a data input terminal, an enable input terminal operable to receive a memory element enabling signal, and a data output terminal. The input selection circuit is coupled to the memory element, and includes an input selection circuit input terminal, and an input selection terminal operable to receive an input selection signal. An output signal at the data output terminal of the memory element is alternately responsive and non-responsive to an input signal applied to the input selection circuit input terminal depending upon the input selection signal and memory enabling signal. The output path is coupled to the data output terminal of the memory element and operable to provide the data to the second clock domain circuit portion.